(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of routing multiple layers of metal.
(2) Description of the Prior Art
Ever increasingly complex and densely packaged semiconductor devices require extensive networks of interconnect metal, a requirement that is especially demanding in the design of standard cell and gate array containing devices in view of the repetitive nature of these structures.
The demands of creating interconnect metal is further driven by demands of creating designs such as gate arrays in basic patterns after which multiple of these patterns can be interconnected to create interconnections that are specifically customer dependent and by thereby creating specialized and unique customer designs. This provides a cost-effective method of creating high-density, high-performance customized devices that perform logic functions in addition to providing storage capabilities and functions of digital signal processing.
The requirements of improving device performance can only be met by increasing device density, an aspect of creating semiconductor devices that typically results in creating overlying layers of interconnect metal. These overlying layers of interconnect metal use multiple layers of metal, adjacent layers being interconnected by interfacing via connections.
The design of more complex and more densely spaced interconnect traces is constrained by limitations imposed by the device elements with which the interconnect metal interfaces. These constraints may be constraints of thermal heat dissipation or constraints of device performance and device miniaturization. With minimization of device elements, the interconnect traces are as a natural consequence also closer spaced while the number of overlying layers of interconnect metal simultaneously continues to expand. From this it is not difficult to conclude that constraints arise between overlying layers of metal and the vias that are used to provide interconnections between adjacent overlying layers of interconnect. Since the vias typically extend in a vertical direction, perpendicularly intersecting with the layers of interconnects to which the vias are connected, it must be expected that the placing of the vias provides a challenge. Incorrect placement of vias will readily lead to shorting of overlying layers that may or may not be adjacent layers.
A method is therefore required that provides for the creation of interconnect vias for multiple layers of overlying metal such that shorts and other device malfunctions of a reliability nature are avoided.
U.S. Pat. No. 5,987,241 (Goldberg et al.) shows routing techniques.
U.S. Pat. No. 5,990,502 (Park) shows an architecture with metallization routing tracks.
U.S. Pat. No. 6,091,090 (Gheewala) shows a power and signal routing technique.
U.S. Pat. No. 5,1923,098 (Yao et al.) shows a routing method.
U.S. Pat. No. 5,923,059 (Gheewala) reveals a cell and routing scheme.